An increasing number of LSIs in recent years, such as those in multimedia systems and operating systems, need much memory (large-capacity memory) for processing. However, the capacity of the memory capable of being mounted on-chip on an LSI is often smaller than a required memory capacity. In such a case, a dedicated memory LSI is connected to the outside of the LSI for performing a desired process. In such a configuration, accesses to the external memory LSI are sometimes made from a plurality of circuits. In a memory control circuit, for example, arbitration control of accesses from a plurality of circuits is performed. Further, in recent years, a clock synchronous type dynamic random access memory (a synchronous DRAM, which is abbreviated as “SDRAM”) has been in wide spread use.
FIG. 1 is a timing chart for explaining a read access to the SDRAM. In the read access, an ACTIVE command, which provides a row (ROW) address of the data to be accessed, is first issued. Next, a READ command, which provides a column (COLUMN) address of the data to be accessed, is issued. After a predetermined delay (a latency), read data D1 is read out from a data terminal DQ. Referring to FIG. 1, a NOP command indicates a state where no command is issued, and a PRE command is a command that instructs precharging of a bit line. FIG. 1 shows operation timings for the read access. On the other hand, a ROW address is provided by using the ACTIVE command and a COLUMN address is provided by using a WRITE command in the case of a write access.
In the memory control circuit that controls accesses from the circuits operated with a same clock, the simplest approach to process the accesses utilizes time-division multiplexing of the accesses.
Time-division multiplexing of accesses will be described below to use an example which comprise a circuit A 201 and a circuit B 202 connected to a memory control circuit 203 to share an SDRAM 204, as shown in FIG. 2.
FIG. 3 is a timing chart, when both circuits A 201 and B 202 issues read commands at the same time, to explain how the memory control circuit 203 processes these commands. The memory control circuit 203 first processes the read access from the circuit A 201 (operation timings of the read access is the same as those in FIG. 1). Next, the memory control circuit 203 processes the read access from the circuit B 202 (operation timings of the read access is the same as those in FIG. 1).
Though time-division multiplexing of the accesses is extremely simple as described above, an access time corresponding to the number of the circuits connected to the memory control circuit 203 is required.
As another approach to process accesses from a plurality of circuits, an interleaving method is also employed. In the interleaving method, a structure capable of controlling respective banks independently is presupposed. In the interleaving method, a memory space to be used by each of the circuits is assigned to each bank capable of being independently controlled. The memory space to be used by the circuit A 201, for example, is assigned to a bank 1, while the memory space to be used by the circuit B 202 is assigned to a bank 2.
FIG. 4 is a timing chart to illustrate the access example from the memory control circuit 203 using the interleaving method. As shown in FIG. 4, by overlapping the respective accesses in the interleaving method, overall processing is sped up. Referring to FIG. 4, following the ACTIVE, NOP, and READ commands for a read access from the circuit A, the ACTIVE, NOP, and READ commands are issued for a read access from the circuit B. During a cycle of the NOP command in the read access from the circuit B, read data D1 corresponding to the read access from the circuit A is read out from a DQ terminal. Then, two cycles later than this cycle, read data D2 corresponding to the read access from the circuit B is read out from the DQ terminal.
Referring to FIG. 3, 14 cycles are spent for the read accesses from the circuits A and B. Referring to FIG. 4, the number of cycles for the read accesses from the circuits A and B is shortened to 10 cycles. It can be seen that the speed of the processing the overall accesses is increased to 1.4 times.
A configuration in which, when accesses from a plurality of circuits are managed by one memory, memory spaces to be accessed by the respective circuits are arranged at different addresses, has been also wide-spread use.